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| copyright 1995 by dallas semiconductor corporation. all rights reserved. for important information regarding patents and other intellectual property rights, please refer to dallas semiconductor data books. ds80c310 highspeed micro ds80c310 preliminary 031296 1/21 features ? 80c32 compatible 8051 pin and instruction set compatible full duplex serial port three 16bit timer/counters 256 bytes scratchpad ram multiplexed address/data bus addresses 64kb rom and 64kb ram ? highspeed architecture 4 clocks/machine cycle (8051 = 12) runs dc to 33 mhz clock rates singlecycle instruction in 121 ns dual data pointer optional variable length movx to access fast/ slow ram /peripherals ? 10 total interrupt sources with 6 external ? internal power on reset circuit ? upwardly compatible with the ds80c320 ? available in 40pin pdip, 44pin plcc, and 44pin tqfp description the ds80c310 is a fast 80c31/80c32 compatible microcontroller. it features a redesigned processor core without wasted clock and memory cycles. as a result, it executes every 8051 instruction between 1.5 and 3 times faster than the original architecture for the same crystal speed. typical applications will see a speed improvement of 2.5 times using the same code and the same crystal. the ds80c310 offers a maximum crystal speed of 33 mhz, resulting in apparent execution speeds of 82.5 mhz (approximately 2.5x). package outline gnd ea p3.7/rd p3.6/wr p3.3/int1 p3.2/int0 p1.7/int5 p1.5/int3 psen dallas ds80c310 vcc ad0 (p0.0) ad1 (p0.1) ad2 (p0.2) ad3 (p0.3) ad4 (p0.4) ad5 (p0.5) ad6 (p0.6) ad7 (p0.7) ale a15 (p2.7) a14 (p2.6) a13 (p2.5) a12 (p2.4) a11 (p2.3) a10 (p2.2) a9 (p2.1) a8 (p2.0) p1.0/t2 p1.1/t2ex p1.2 p1.3 p1.4/int2 p1.6/int4 rst p3.0/rxd0 p3.1/txd0 p3.4/t0 p3.5/t1 xtal2 xtal1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 40pin dip dallas ds80c310 44pin plcc 140 6 7 17 29 39 18 28 dallas ds80c310 44pin tqfp 23 33 22 12 34 44 111
ds80c310 031296 2/21 the ds80c310 is pin compatible with the standard 80c32 and includes standard resources such as three timer/counters, 256 bytes of ram, and a serial port. it also provides dual data pointers (dptrs) to speed block data memory moves. it also can adjust the speed of movx data memory access between two and nine machine cycles for flexibility in selecting external memory and peripherals. the ds80c310 offers upward compatibility with the ds80c320. ordering information: part number package max. clock speed temperature range ds80c310mcg 40pin plastic dip 25 mhz 0 c to 70 c ds80c310qcg 44pin plcc 25 mhz 0 c to 70 c ds80c310ecg 44pin tqfp 25 mhz 0 c to 70 c ds80c310mcl 40pin plastic dip 33 mhz 0 c to 70 c ds80c310qcl 44pin plcc 33 mhz 0 c to 70 c ds80c310ecl 44pin tqfp 33 mhz 0 c to 70 c ds80c310 block diagram figure 1 p1.0p1.7 p3.0p3.7 port 1 port 3 interrupt ad0ad7 p2.0p2.7 clocks and logic memory control interrupt reg. instruction decode psw stack pointer alu reg. 2 b register accumulator alu reg. 1 alu oscillator power control reg. reset control 256 bytes sfr 8 ram dptr1 pc addr. reg. buffer pc increment prog. counter dptr0 port 0 port 2 timer 2 timer 1 timer 0 port latch serial port 0 port latch timed access sfr ram address port latch address bus data bus xtal2 xtal1 ale psen rst ds80c310 031296 3/21 pin description table 1 dip plcc tqfp signal name description 40 44 38 v cc v cc +5v. 20 22, 23, 1 16, 17, 39 gnd gnd digital circuit ground. 9 10 4 rst rst input . the rst input pin contains a schmitt voltage input to recognize external active high reset inputs. the pin also employs an internal pulldown resistor to allow for a combination of wired or external reset sources. 18 19 20 21 14 15 xtal2 xtal1 xtal1, xtal2 the crystal oscillator pins xtal1 and xtal2 provide support for parallel resonant, at cut crystals. xtal1 acts also as an input in the event that an external clock source is used in place of a crystal. xtal2 serves as the output of the crystal amplifier. 29 32 26 psen psen output . the program store enable output. this signal is commonly connected to external rom memory as a chip enable. psen is active low. psen is driven high when data memory (ram) is being accessed through the bus and during a reset condition. 30 33 27 ale ale output . the address latch enable output functions as a clock to latch the external address lsb from the multiplexed address/data bus on port 0. this signal is commonly connected to the latch enable of an external 373 family transparent latch. ale is forced high when the ds80c310 is in a reset condition. 39 38 37 36 35 34 33 32 43 42 41 40 39 38 37 36 37 36 35 34 33 32 31 30 ad0 (p0.0) ad1 (p0.1) ad2 (p0.2) ad3 (p0.3) ad4 (p0.4) ad5 (p0.5) ad6 (p0.6) ad7 (p0.7) ad07 (port 0) i/o . port 0 is the multiplexed address/data bus. during the time when ale is high, the lsb of a memory address is presented. when ale falls to a logic 0, the port transitions to a bidirectional data bus. this bus is used to read external rom and read/write external ram memory or peripherals. port 0 has no true port latch and can not be written directly by software. the reset condition of port 0 is high. 18 29 4044 13 p1.0p1.7 port 1 i/o . port 1 functions as both an 8bit bidirectional i/o port and an alternate functional interface for timer 2 i/o and new exter- nal interrupts. the reset condition of port 1 is with all bits at a logic 1. in this state, a weak pullup holds the port high. this condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pullup. when software writes a 0 to any port pin, the ds80c310 will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pullup. once the momentary strong driver turns off, the port once again becomes the output high (and input) state. the alternate modes of port 1 are outlined as follows: ds80c310 031296 4/21 dip description signal name tqfp plcc 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 40 41 42 43 44 1 2 3 port alternate function p1.0 t2 external i/o for timer/counter 2 p1.1 t2ex timer/counter 2 capture/reload trigger p1.2 none (ds80c320 has a serial port rxd) p1.3 none (ds80c320 has a serial port txd) p1.4 int2 external interrupt 2 (positive edge detect) p1.5 int3 external interrupt 3 (negative edge detect) p1.6 int4 external interrupt 4 (positive edge detect) p1.7 int5 external interrupt 5 (negative edge detect) 21 22 23 24 25 26 27 28 24 25 26 27 28 29 30 31 18 19 20 21 22 23 24 25 a8 (p2.0) a9 (p2.1) a10 (p2.2) a11 (p2.3) a12 (p2.4) a13 (p2.5) a14 (p2.6) a15 (p2.7) a815 (port 2) output . port 2 serves as the msb for external addressing. p2.7 is a15 and p2.0 is a8. the ds80c310 will auto- matically place the msb of an address on p2 for external rom and ram access. although port 2 can be accessed like an ordinary i/o port, the value stored on the port 2 latch will never be seen on the pins (due to memory access). therefore writing to port 2, in software is only useful for the instructions movx a, @ ri or movx @ ri, a. these instructions use the port 2 internal latch to supply the external address msb. in this case, the port 2 latch value will be supplied as the address information. 1017 11, 1319 5, 713 p3.0p3.7 port 3 i/o. port 3 functions as both an 8bit bidirectional i/o port and an alternate functional interface for external interrupts, serial port 0, timer 0 and 1 inputs, rd and wr strobes. the reset condition of port 3 is with all bits at a logic 1. in this state, a weak pullup holds the port high. this condition also serves as an input mode, since any external circuit that writes to the port will over- come the weak pullup. when software writes a 0 to any port pin, the ds80c310 will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, fol- lowed by a weaker sustaining pullup. once the momentary strong driver turns off, the port once again becomes both the out- put high and input state. the alternate modes of port 3 are outlined below. 10 11 12 13 14 15 16 17 11 13 14 15 16 17 18 19 5 7 8 9 10 11 12 13 port alternate mode p3.0 rxd0 serial port 0 input p3.1 txd0 serial port 0 output p3.2 int0 external interrupt 0 p3.3 int1 external interrupt 1 p3.4 t0 timer 0 external input p3.5 t1 timer 1 external input p3.6 wr external data memory write strobe p3.7 rd external data memory read strobe 31 35 29 ea ea input. this pin must be connected to ground for proper operation. 12 34 6 28 nc nc reserved . these pins should not be connected. they are reserved for use with future devices in this family. ds80c310 031296 5/21 compatibility the ds80c310 is a fully static cmos 8051 compatible microcontroller designed for high performance. in most cases the ds80c310 can drop into an existing socket for the 80c31 or 80c32 to improve the operation signifi- cantly. in general, software written for existing 8051 based systems works without modification on the ds80c310. the exception is critical timing since the highspeed micro performs its instructions much faster than the original for any given crystal selection. the ds80c310 runs the standard 8051 family instruction set and is pin compatible with dip, plcc or tqfp pack- ages. the ds80c310 is a streamlined version of the ds80c320. it maintains upward compatibility but has fewer peripherals. the ds80c310 provides three 16bit timer/counters, a fullduplex serial port, and 256 bytes of direct ram. i/o ports have the same operation as a standard 8051 prod- uct. timers will default to a 12 clock per cycle operation to keep their timing compatible with original 8051 family systems. however, timers are individually program- mable to run at the new 4 clocks per cycle if desired. the ds80c310 provides several new hardware func- tions that are controlled by special function registers. a summary of the special function registers is provided in table 2. performance overview the ds80c310 features a highspeed 8051 compatible core. higher speed comes not just from increasing the clock frequency, but from a newer, more efficient design. this updated core does not have the dummy memory cycles that are present in a standard 8051. a conven- tional 8051 generates machine cycles using the clock frequency divided by 12. in the ds80c310, the same machine cycle takes four clocks. thus the fastest instruction, 1 machine cycle, executes three times faster for the same crystal frequency. note that these are identical instructions. the majority of instructions on the ds80c310 will see the full 3 to 1 speed improve- ment. some instructions will get between 1.5 and 2.4 to 1 improvement. all instructions are faster than the origi- nal 8051. the numerical average of all opcodes gives approxi- mately a 2.5 to 1 speed improvement. improvement of individual programs will depend on the actual instruc- tions used. speed sensitive applications would make the most use of instructions that are three times faster. however, the sheer number of 3 to 1 improved opcodes makes dramatic speed improvements likely for any code. these architecture improvements and 0.8 m m cmos produce a peak instruction cycle in 121 ns (8.25 mips). the dual data pointer feature also allows the user to eliminate wasted instructions when moving blocks of memory. instruction set summary all instructions in the ds80c310 perform the same functions as their 8051 counterparts. their effect on bits, flags, and other status functions is identical. how- ever, the timing of each instruction is different. this applies both in absolute and relative number of clocks. for absolute timing of realtime events, the timing of software loops can be calculated using a table in the highspeed microcontroller user's guide. however, counter/timers default to run at the older 12 clocks per increment. in this way, timerbased events occur at the standard intervals with software executing at higher speed. timers optionally can run at 4 clocks per incre- ment to take advantage of faster processor operation. the relative time of two instructions might be different in the new architecture than it was previously. for exam- ple, in the original architecture, the amovx a, @dptro instruction and the amov direct, directo instruction used two machine cycles or 24 oscillator cycles. therefore, they required the same amount of time. in the ds80c310, the movx instruction takes as little as two machine cycles or eight oscillator cycles but the amov direct, directo uses three machine cycles or 12 oscillator cycles. while both are faster than their original counter- parts, they now have different execution times. this is because the ds80c310 usually uses one instruction cycle for each instruction byte. the user concerned with precise program timing should examine the timing of each instruction for familiarity with the changes. note that a machine cycle now requires just four clocks, and provides one ale pulse per cycle. many instructions require only one cycle, but some require five. in the orig- inal architecture, all were one or two cycles except for mul and div. refer to the highspeed microcontroller user's guide for details and individual instruction tim- ing. ds80c310 031296 6/21 special function registers special function registers (sfrs) control most special features of the ds80c310. the highspeed microcontroller user's guide describes all sfrs. functions that are not part of the standard 80c32 are in bold. special function registers table 2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address sp 81h dpl 82h dph 83h dpl1 84h dph1 85h dps 0 0 0 0 0 0 0 sel 86h pcon smod smod0 gf1 gf0 stop idle 87h tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 88h tmod gate c/t m1 m0 gate c/t m1 m0 89h tl0 8ah tl1 8bh th0 8ch th1 8dh ckcon t2m t1m t0m md2 md1 md0 8eh p1 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 90h exif ie5 ie4 ie3 ie2 91h scon sm0/fe sm1 sm2 ren tb8 rb8 ti ri 98h sbuf 99h p2 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 a0h ie ea et2 es0 et1 ex1 et0 ex0 a8h saddr0 a9h p3 p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 b0h ip pt2 ps0 pt1 px1 pt0 px0 b8h saden0 b9h status 0 hip lip 1 1 1 1 1 c5h t2con tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 c8h t2mod t2oe dcen c9h rcap2l cah rcap2h cbh tl2 cch th2 cdh psw cy ac f0 rs1 rs0 ov fl p d0h wdcon por d8h acc e0h eie ex5 ex4 ex3 ex2 e8h b f0h eip px5 px4 px3 px2 f8h ds80c310 031296 7/21 memory access the ds80c310 contains no onchip rom, and 256 bytes of scratchpad ram. offchip memory is accessed using the multiplexed address/data bus on p0 and the msb address on p2. timing diagrams are provided in the electrical specifications. program memory (rom) is accessed at a fixed rate determined by the crystal frequency and the actual instructions. as mentioned above, an instruction cycle requires four clocks. data memory (ram) is accessed according to a variable speed movx instruction as described below. stretch memory cycle the ds80c310 allows the application software to adjust the speed of data memory access. the micro is capable of performing the movx in as few as two instruction cycles. however, this value can be stretched as needed so that both fast memory and slow memory or peripher- als can be accessed with no glue logic. even in high speed systems, it may not be necessary or desirable to perform data memory access at full speed. in addition, there are a variety of memory mapped peripherals such as lcd displays or uarts that are not fast. the stretch movx is controlled by the clock control register at sfr location 8eh as described below. this allows the user to select a stretch value between zero and seven. a stretch of zero will result in a two machine cycle movx. a stretch of seven will result in a movx of nine machine cycles. software can dynamically change this value depending on the particular memory or peripheral. on reset, the stretch value will default to a one resulting in a three cycle movx. therefore, ram access will not be performed at full speed. this is a convenience to existing designs that may not have fast ram in place. when maximum speed is desired, the software should select a stretch value of zero. when using very slow ram or peripherals, a larger stretch value can be selected. note that this affects data memory only and the only way to slow program memory (rom) access is to use a slower crystal. using a stretch value between one and seven causes the microcontroller to stretch the read/write strobe and all related timing. this results in a wider read/write strobe allowing more time for memory/peripherals to respond. the timing of the variable speed movx is shown in the electrical specifications. note that full speed access is not the reset default case. table 3 shows the resulting strobe widths for each stretch value. the memory stretch is implemented using the clock control special function register at sfr loca- tion 8eh. the stretch value is selected using bits ckcon.20. in the table, these bits are referred to as m2 through m0. the first stretch (default) allows the use of common 120 ns or 150 ns rams without dramatically lengthening the memory access. data memory cycle stretch values table 3 ckcon.20 memory cycles rd or wr strobe strobe width time m2 m1 m0 memory cycles rd or wr strobe width in clocks @ 25 mhz @ 33 mhz 0 0 0 2 2 80 ns 60 ns 0 0 1 3 (default) 4 160 ns 121 ns 0 1 0 4 8 320 ns 242 ns 0 1 1 5 12 480 ns 364 ns 1 0 0 6 16 640 ns 485 ns 1 0 1 7 20 800 ns 606 ns 1 1 0 8 24 960 ns 727 ns 1 1 1 9 28 1120 ns 848 ns ds80c310 031296 8/21 dual data pointer data memory block moves can be accelerated using the ds80c310 dual data pointer (dptr). the stan- dard 8032 dptr is a 16bit value that is used to address offchip data ram or peripherals. in the ds80c310, the standard data pointer is called dptr and is located at sfr addresses 82h and 83h. these are the standard locations. no modification of standard code is needed to use dptr. the new dptr is located at sfr 84h and 85h and is called dptr1. the dptr select bit (dps) chooses the active pointer and is located at the lsb of the sfr location 86h. no other bits in register 86h have any effect and are set to 0. the user switches between data pointers by toggling the lsb of register 86h. the increment (inc) instruction is the fast- est way to accomplish this. all dptrrelated instruc- tions use the currently selected dptr for any activity. therefore only one instruction is required to switch from a source to a destination address. using the dual data pointer saves code from needing to save source and destination addresses when doing a block move. once loaded, the software simply switches between dptr0 and 1. the relevant register locations are as follows. dpl 82h low byte original dptr dph 83h high byte original dptr dpl1 84h low byte new dptr dph1 85h high byte new dptr dps 86h dptr select (lsb) stop mode enhancements setting bit 1 of the power control register (pcon; 87h) invokes the stop mode. stop mode is the lowest power state since it turns off all internal clocking. the i cc of a standard stop mode is approximately 1 m a (but is speci- fied in the electrical specifications). the cpu will exit stop mode from an external interrupt or a reset condi- tion. internally generated interrupts are not useful since they require clocking activity. the ds80c310 allows a resume from stop using a int25, which are edge triggered interrupts. the startup timing is managed by an internal crystal counter. a delay of 65,536 clocks occurs to give the crystal enough time to start and stabilize. peripheral overview the ds80c310 provides the same peripheral functions as the standard 80c32. it is compatible with the ds80c320 but does not offer all of the peripherals. timer rate control there is one important difference between the ds80c310 and 8051 regarding timers. the original 8051 used 12 clocks per cycle for timers as well as for machine cycles. the ds80c310 architecture normally uses 4 clocks per machine cycle. however, in the area of timers and serial ports, the ds80c310 will default to 12 clocks per cycle on reset. this allows existing code with realtime dependencies such as baud rates to operate properly. if an application needs higher speed timers or serial baud rates, the user can select individual timers to run at the 4 clock rate. the clock control register (ckcon; 8eh) determines these timer speeds. when the relevant ckcon bit is a logic 1, the ds80c310 uses 4 clocks per cycle to generate timer speeds. when the bit is a 0, the ds80c310 uses 12 clocks for timer speeds. the reset condition is a 0. ckcon.5 selects the speed of timer 2. ckcon.4 selects timer 1 and ckcon.3 selects timer 0. note that unless a user desires very fast timing, it is unnecessary to alter these bits. note that the timer con- trols are independent. power on reset the ds80c310 will hold itself in reset during a power up until 65,536 clock cycles have elapsed. the poweron reset used by the ds80c310 differs somewhat from other members of the highspeed microcontroller fam- ily. the crystal oscillator may start anywhere between 1.0v and 4.5v, but is not specified. this eliminates the need for an rc reset circuit. for voltage specific preci- sion brownout detection, an external component will be needed. when the device goes through a power on reset, the por flag will be set in the wdcon (d8h) reg- ister at bit 6. interrupts the ds80c310 provides 10 interrupt sources with two priority levels. software can assign high or low priority to all sources. all interrupts that are new to the 8051 have a lower natural priority than the originals. ds80c310 031296 9/21 interrupt sources and priorities table 4 name description vector natural priority int0 external interrupt 0 03h 1 tf0 timer 0 0bh 2 int1 external interrupt 1 13h 3 tf1 timer 1 1bh 4 scon ti or ri from the serial port 23h 5 tf2 timer 2 2bh 6 int2 external interrupt 2 43h 7 int3 external interrupt 3 4bh 8 int4 external interrupt 4 53h 9 int5 external interrupt 5 5bh 10 ds80c310 031296 10/21 absolute maximum ratings* voltage on any pin relative to ground 0.3v to +7.0v operating temperature 0 c to 70 c storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (0 c to 70 c; v cc =4.0v to 5.5v) parameter symbol min typ max units notes supply voltage v cc 4.0 5.0 5.5 v 1 supply current active mode @ 33 mhz i cc 30 ma 2 supply current idle mode @ 33 mhz i idle 15 ma 3 supply current stop mode i stop 1 m a 4 input low level v il 0.3 +0.8 v 1 input high level v ih 2.0 v cc +0.3 v 1 input high level xtal1 and rst v ih2 3.5 v cc +0.3 v 1 output low voltage ports 1, 3 @ i ol =1.6 ma v ol1 0.15 0.45 v 1 output low voltage port 0, 2, ale, psen @ i ol =3.2 ma v ol2 0.15 0.45 v 1, 5 output high voltage ports 1, 3, ale and psen @ i oh = 50 m a v oh1 2.4 v 1, 6 output high voltage @ i oh =1.5 ma ports 1, 3 v oh2 2.4 v 1, 7 output high voltage ports 0, 2, ale, psen @ i oh = 8 ma v oh3 2.4 v 1, 5 input low current ports 1, 3 @ 0.45v i il 55 m a transition current from 1 to 0 ports 1, 3 @ 2v i tl 650 m a 8 input leakage port 0, bus mode i l 300 300 m a 9 rst pulldown resistance r rst 50 170 k w notes for dc electrical characteristics: all parameters apply to both commercial and industrial temperature operation unless otherwise noted. 1. all voltages are referenced to ground. 2. active current is measured with a 33 mhz clock source driving xtal1, v cc =rst=5.5v, all other pins discon- nected. 3. idle mode current is measured with a 33 mhz clock source driving xtal1, v cc =5.5v, rst at ground, all other pins disconnected. ds80c310 031296 11/21 4. stop mode current measured with xtal1 and rst grounded, v cc =5.5v, all other pins disconnected. 5. when addressing external memory. 6. rst=v cc . this condition mimics operation of pins in i/o mode. 7. during a 0 to 1 transition, a oneshot drives the ports hard for two clock cycles. this measurement reflects port in transition mode. 8. ports 1, 2, and 3 source transition current when being pulled down externally. it reaches its maximum at approximately 2v. 9. 0.45 ds80c310 031296 13/21 movx characteristics (0 c to 70 c; v cc =4.0v to 5.5v) parameter symbol variable clock units stretch parameter symbol min max units stretch data access ale pulse width t llhl2 1.5t clcl 5 2t clcl 5 ns t mcs =0 t mcs >0 address hold after ale low for movx write t llax2 0.5t clcl 5 t clcl 5 ns t mcs =0 t mcs >0 rd pulse width t rlrh 2t clcl 5 t mcs 10 ns t mcs =0 t mcs >0 wr pulse width t wlwh 2t clcl 5 t mcs 10 ns t mcs =0 t mcs >0 rd low to valid data in t rldv 2t clcl 20 t mcs 20 ns t mcs =0 t mcs >0 data hold after read t rhdx 0 ns data float after read t rhdz t clcl 5 2t clcl 5 ns t mcs =0 t mcs >0 ale low to valid data in t lldv 2.5t clcl 20 t clcl+ t mcs 40 ns t mcs =0 t mcs >0 port 0 address to valid data in t avdv1 3t clcl 20 1.5t clcl+ t mcs 20 ns t mcs =0 t mcs >0 port 2 address to valid data in t avdv2 3.5t clcl 20 2t clcl+ t mcs 20 ns t mcs =0 t mcs >0 ale low to rd or wr low t llwl 0.5t clcl 5 t clcl 5 0.5t clcl +5 t clcl +5 ns t mcs =0 t mcs >0 port 0 address to rd or wr low t avwl1 t clcl 5 2t clcl 5 ns t mcs =0 t mcs >0 port 2 address to rd or wr low t avwl2 1.5t clcl 10 2.5t clcl 10 ns t mcs =0 t mcs >0 data valid to wr transition t qvwx 5 ns t mcs =0 data hold after write t whqx t clcl 5 2t clcl 5 ns t mcs =0 t mcs >0 rd low to address float t rlaz 0.5t clcl 5 ns rd or wr high to ale high t whlh 0 t clcl 5 10 t clcl +5 ns t mcs =0 t mcs >0 note: t mcs is a time period related to the stretch memory cycle selection. the following table shows the value of t mcs for each stretch selection. m2 m1 m0 movx cycles t mcs 0 0 0 2 machine cycles 0 0 0 1 3 machine cycles (default) 4 t clcl 0 1 0 4 machine cycles 8 t clcl 0 1 1 5 machine cycles 12 t clcl 1 0 0 6 machine cycles 16 t clcl 1 0 1 7 machine cycles 20 t clcl 1 1 0 8 machine cycles 24 t clcl 1 1 1 9 machine cycles 28 t clcl ds80c310 031296 14/21 external clock characteristics (0 c to 70 c; v cc =4.0v to 5.5v) parameter symbol min typ max units notes clock high time t chcx 10 ns clock low time t clcx 10 ns clock rise time t clcl 5 ns clock fall time t chcl 5 ns serial port mode 0 timing characteristics (0 c to 70 c; v cc =4.0v to 5.5v) parameter symbol min typ max units notes serial port clock cycle time sm2=0, 12 clocks per cycle sm2=1, 4 clocks per cycle t xlxl 12t clcl 4t clcl ns ns output data setup to clock rising sm2=0, 12 clocks per cycle sm2=1, 4 clocks per cycle t qvxh 10t clcl 3t clcl ns ns output data hold from clock rising sm2=0, 12 clocks per cycle sm2=1, 4 clocks per cycle t xhqx 2t clcl t clcl ns ns input data hold after clock rising sm2=0, 12 clocks per cycle sm2=1, 4 clocks per cycle t xhdx t clcl t clcl ns ns clock rising edge to input data valid sm2=0, 12 clocks per cycle sm2=1, 4 clocks per cycle t xhdv 11t clcl 3t clcl ns ns explanation of ac symbols in an effort to remain compatible with the original 8051 family, this device specifies the same parameters as such devices, using the same symbols. for complete- ness, the following is an explanation of the symbols. t time a address c clock d input data h logic level high l logic level low i instruction p psen q output data rrd signal v valid wwr signal x no longer a valid logic level z tristate ds80c310 031296 15/21 external program memory read cycle ale psen port 0 port 2 address a8a15 out address a8a15 out address a0a7 instruction in address a0a7 t aviv2 t lhll t lliv t avll t plph t pliv t llpl t plaz t llax1 t pxiz t pxix t aviv1 external data memory read cycle ale psen rd port 0 port 2 address a8a15 out data in instruction in address a0a7 address a0a7 t lldv t whlh t avwl1 t rlrh t rldv t rhdz t rhdx t avll t rlaz t llwl t llax1 t avdv1 t avwl2 t avdv2 ds80c310 031296 16/21 data memory write cycle ale wr psen port 0 port 2 address a8a15 out data out address address instruction t wlwh t avwl1 t whqx t avll t llax2 t llwl t whlh t qvwx in a0a7 a0a7 t avwl2 data memory write with stretch=1 psen wr clk ale port 0 port 2 c1 c2 c3 c4 c1 c2 c3 c4 c1 c2 c3 c4 c1 c2 c3 c4 c1 c2 c3 c4 d0d7 a0a7 d0d7 d0d7 d0d7 a0a7 a0a7 a0a7 a8a15 a8a15 a8a15 a8a15 last cycle of previous instruction first machine cycle second machine cycle third machine cycle next instruction machine cycle movx instruction movx instruction address next instr. address movx data address next instruction read movx instruction movx data ds80c310 031296 17/21 data memory write with stretch=2 c1 c2 c3 c4 c1 c2 c3 c4 c1 c2 c3 c4 c1 c2 c3 c4 c1 c2 c3 c4 c1 c2 c3 c4 d0d7 a0a7 d0d7 d0d7 d0d7 a0a7 a0a7 a0a7 a8a15 a8a15 a8a15 a8a15 psen wr clk ale port 0 port 2 movx instruction address next instr. address movx data address next instruction read movx instruction movx data next instruction machine cycle movx instruction last cycle of previous instruction first machine cycle second machine cycle third machine cycle fourth machine cycle four cycle data memory write stretch value=2 external clock drive xtal1 t clcl t clch t chcl t clcx t chcx ds80c310 031296 18/21 serial port mode 0 timing psen psen transmit receive ale write to sbuf rxd data out txd clock ti write to scon to clear ri rxd data in txd clock ri serial port 0 (synchronous mode) high speed operation sm2=1=>txd clock=xtal/4 serial port 0 (synchronous mode) sm2=0=>txd clock=xtal/12 transmit receive ale rxd txd ti write to scon to clear ri rxd data in txd clock ri write to sbuf clock data out d0 d1 d7 d6 d0 d1 d7 d6 d0 d1 d2 d3 d4 d5 d7 d8 d0 d1 d2 d3 d4 d5 d7 d8 t qvxl t xhqx t xlxl t xhdv t xhdx 1/(xtal freq/12) ds80c310 031296 19/21 40pin pdip (600 mil) all dimensions are in inches. pkg 40-pin dim min max a 0.200 a1 0.015 a2 0.140 0.160 b 0.014 0.022 c 0.008 0.012 d 1.980 2.085 e 0.600 0.625 e1 0.530 0.555 e 0.090 0.110 l 0.115 0.145 eb 0.600 0.700 56g5000000 ds80c310 031296 20/21 44pin plcc pkg 44pin dim min max a 0.165 0.180 a1 0.090 0.120 a2 0.020 b 0.026 0.033 b1 0.013 0.021 c 0.009 0.012 ch1 0.042 0.048 d 0.685 0.695 d1 0.650 0.656 d2 0.590 0.630 e 0.685 0.695 e1 0.650 0.656 e2 0.590 0.630 e1 0.050 bsc n 44 56g4003001 1 ds80c310 031296 21/21 44pin tqfp pkg 44pin dim min max a 1.20 a1 0.05 0.15 a2 0.95 1.05 d 11.80 12.20 d1 10.00 bsc e 11.80 12.20 e1 10.00 bsc l 0.45 0.75 e 0.80 bsc b 0.30 0.45 c 0.09 0.20 56g4012001 |
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